1. Field of the Invention
The present invention generally relates to a non-planar Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) made on semiconductor on insulator (SOI) substrates wherein the MOSFET has a stress enhancement layer. In particular, the invention relates to FinFETs with a merged source drain region in which the merged region is recessed and a stress adjustment layer which is deposited over the source drain region and a gate stack of the FinFET.
2. Description of Related Art
In a paper entitled “A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors,” by T. Ghani et al. in IEDM 2003 a nitride layer to create tensile stress in nMOS devices and recessed SiGe source drains to create compressive stress in pMOS devices is disclosed. The devices are planar on a bulk silicon substrate.
In a paper entitled “Dual Stress Liner for High Performance sub-45 nm Gate Length SOI CMOS Manufacturing,” by H. S. Yang et al. in IEEE International Electronic Device Meeting 2004, a planar device built on an SOI substrate using a dual stress liner (tensile to nMOS and compressive to pMOS) is disclosed.
In a paper entitled “Integration and Optimization of Embedded SiGe, Compressive and Tensile Stressed Liner Films, and Stress Memorization in Advanced SOI CMOS Technologies,” in IEDM 2005, M. Hortsmann discloses an optimized 4-way stress integration on partially-depleted SOI (PD-SOI) CMOS planar substrate. An embedded-SiGe process and a compressive-stressed liner film are used to induce compressive strain in the PMOS (PMOS “stressors”). A stress memorization process and a tensile-stressed liner film are used to induce tensile strain in the NMOS (NMOS “stressors”).
U.S. Patent Application 2009/0152638 A1 by Belyansky et al. filed on Dec. 13, 2009 describes a Complimentary Metal Oxide Semiconductor (CMOS) planar transistor in which the pFETs have a compressive nitride stress layer and the nFETs have a tensile nitride layer. In addition, the pFET and nFET nitride layers can be topped by a compressive oxide layer and tensile oxide layer, respectively.
In U.S. published patent application No. 2006/0261411 A1, Hareland et al. disclose a tri-gate device with a stress film which completely surrounds the channel (i.e. is beneath the channel, too).
In a paper entitled “FinFET SRAM Process Technology for hp32 nm Node and Beyond,” by Atsushi Yagishita published in 2007 IEEE ICICDT07 it is disclosed that a reduction in FinFET width deteriorates current drive and leads to high parasitic resistance (increased source drain series resistance). The article states raised source drains reduce parasitic resistance, lower S/D series resistance and improves drive current. The article warns against merging raised source drains (i.e. epi-merge process) because (1) it increases the capacitance between the gate and the source/drain, and (2) it increases the chance of a short circuit between adjacent nFET fins and pFET fins.
In a paper entitled “Investigation of FinFET devices for 32 nm Technologies and Beyond,” by H. Shang in IEEE 2006 Symposium on VLSI Technology Digest of Technical Papers, October 2006, a FinFET source/drain (S/D) contact scheme is proposed in which individual fins without large S/D landing pads can be later merged by selective epitaxy. According to Shang, multi-gate MOSFETs (such as the FinFET and Tri-gate FET) are potential device candidates for the 32 nm node and beyond. Shang's concerns, however, include the formation of narrow and uniform fins while providing low series resistance from the extension and contact regions of the device. In addition the fins must be placed at a fine pitch to make efficient use of layout area. Previous demonstrations use large S/D landing pads for a simplified contact scheme which Shang claims is unsuitable for a realistic technology. Shang examines spacer formation, raised S/D (RSD) by selective Si epitaxy, silicidation, and an integration scheme of individual fins (without large S/D landing pads) being merged by selective epitaxy. Shang reports there is a tradeoff between increased parasitic capacitance and reduced parasitic resistance.
In a U.S. Pat. No. 7,851,865 B2, Anderson discloses a FinFET on SOI in which the fins are merged by a conductive material (silicide) deposited over an epi layer which in turn is over the fins. Note, that Anderson's epi layer does not merge the fins, instead the silicide merges the fins.
In U.S. published patent application No. 2008/0067613 A1, Anderson et al. discloses a strapping between fins which can involve some raised source drains being taller than others.
In a paper entitled “Challenges and Solutions of FinFET Integration in an SRAM Cell and a Logic Circuit for 22 nm Node and Beyond,” in IEDM 2009 H. Kawaski et al., discloses merged diamond shaped fins.
In a paper entitled “High Performance and High Uniform Gate-All-Around Silicon Nanowire MOSFETs with Wire Size Dependent Scaling,” by S. Bangsaruntip in IEDM 2009 merged source drains on SOI substrate with suspended nanowires (rather than fins) are disclosed.
In U.S. published patent application No. US 2008/0230852 A1, Yu discloses fins in different transistors may be of different heights.